1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. Specifically, the present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) device having high drivability and high reliability.
2. Description of the Prior Art
In recent years, as semiconductor integrated circuit devices with an increased degree of integration, a more effective function, and an increased operation speed have been developed, a dual oxide process in which a thick gate insulating film and a thin gate insulating film are formed in one and the same device has been adopted generally (For example, see Japanese Unexamined Patent Publication No. 2003-31683).
FIGS. 16A through 16C illustrate steps of a conventional method for fabricating a semiconductor device having a CMOS device in the order of fabrication. First, as illustrated with FIG. 16A, in a semiconductor substrate 101 such as silicon, a device isolation region 102 is formed by STI (Shallow Trench Isolation). As a result, in the semiconductor substrate 101, an N-type MOS (Metal Oxide Semiconductor) transistor formation region 111, a P-type MOS transistor formation region 112, and a thick-film transistor (N-type MOS transistor) formation region 113 are formed. Subsequently, over the N-type MOS transistor formation region 111, the P-type MOS transistor formation region 112, and the thick-film transistor region 113, a first silicon oxide (SiO2) film 103 having a thickness of between 3 nm and 10 nm is formed. Next, part of the first SiO2 film 103 over the N-type MOS transistor formation region 111 and the P-type MOS transistor formation region 112 is removed using a photosensitive resist as a mask.
Next, as illustrated with FIG. 16B, a second SiO2 film 104 having a thickness of between 1 nm and 3 nm is formed over the N-type MOS transistor formation region 111 and the P-type MOS transistor formation region 112.
Next, as illustrated with FIG. 16C, the first SiO2 film 103 and the second SiO2 film 104 are nitrided to be changed into silicon oxynitride (SiON) films which are a first gate insulating film 105, a second gate insulating film 106, and a third gate insulating film 107.
After this, over the semiconductor substrate 101 having the first gate insulating film 105, the second gate insulating film 106, and the third gate insulating film 107, a polycrystalline silicon film having a thickness of 100 nm is formed. Next, an N-type impurity is implanted into part of the polycrystalline silicon film formed over the N-type MOS transistor formation region 111 and the thick-film transistor formation region 113, and a P-type impurity is implanted into part of the polycrystalline silicon film formed over the P-type MOS transistor formation region 112. After this, by adopting photolithography and RIE (reactive ion etching), the polycrystalline silicon film, the first gate insulating film 105, the second gate insulating film 106, and the third gate insulating film 107 are sequentially etched. This results in the formation of an N-type MOS transistor having the first gate insulating film 105 and a gate electrode over the N-type MOS transistor formation region 111 of the semiconductor substrate 101, a P-type MOS transistor having the second gate insulating film 106 and a gate electrode over the P-type MOS transistor formation region 112 of the semiconductor substrate 101, and a thick-film transistor having the third gate insulating film 107 and a gate electrode over the thick-film transistor formation region 113 of the semiconductor substrate 101, the thick-film transistor being an N-type MOS transistor.
As described above, according to the conventional method, it is possible to form the first gate insulating film 105 of the N-type MOS transistor and the second gate insulating film 106 of the P-type MOS transistor physically thinner in thickness than the third gate insulating film 107 of the thick-film transistor. Moreover, the N-type impurity is implanted into the gate electrode of the N-type MOS transistor and the P-type impurity is implanted into the gate electrode of the P-type MOS transistor, that is, the different impurities are implanted into the gate electrodes. Therefore, the first gate insulating film 105 of the N-type MOS transistor and the second gate insulating film 106 of the P-type MOS transistor are different from each other in electrical thickness. As a result, it is possible to realize gate insulating films which are respectively suitable for the N-type MOS transistor and the P-type MOS transistor.
However, the above-mentioned conventional semiconductor device has problems as follows. According to the conventional method for fabricating a semiconductor device, the N-type impurity is introduced into the gate electrode of the N-type MOS transistor and the P-type impurity is introduced into the gate electrode of the P-type MOS transistor in order that the gate electrode of the N-type MOS transistor and the gate electrode of the P-type MOS transistor may have different work functions. However, the first gate insulating film 105 of the N-type MOS transistor and the second gate insulating film 106 of the P-type MOS transistor are silicon oxynitride films which are formed in the same step, have the same thickness, and have the same nitrogen concentration. Therefore, if the thickness and the nitrogen concentration of the first gate insulating film 105 of the N-type MOS transistor are optimized, optimization of the thickness and the nitrogen concentration of the second gate insulating film 106 of the P-type MOS transistor is insufficient. This results in the problem that the P-type MOS transistor can not obtain an optimal characteristic.